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data sheet IDT8N3Q001gcd revision a march 6, 2012 1 ?2012 integrated device technology, inc. quad-frequency programmable xo IDT8N3Q001 rev g general description the IDT8N3Q001 is a quad-frequency programmable clock oscillator with very flexible frequency programming capabilities. the device uses idt?s fourth generation femtoclock? ng technology for an optimum of high clock frequency and low phase noise performance. the device accepts 2.5v or 3.3v supply and is packaged in a small, lead-free (rohs 6) 10-lead ceramic 5mm x 7mm x 1.55mm package. besides the four default power-up frequencies set by the fsel0 and fsel1 pins, the IDT8N3Q001 can be programmed via the i 2 c interface to output clock frequencies between 15.476mhz to 866.67mhz and from 975mhz to 1, 300mhz to a very high degree of precision with a frequency step size of 435.9hz n ( n is the pll output divider). since the fsel0 and fsel1 pins are mapped to 4 independent pll m and n divider registers (p, mint, mfrac and n), reprogramming those registers to other frequencies under control of fsel0 and fsel1 is supported. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. features ? fourth generation femtoclock? ng technology ? programmable clock output frequency from 15.476mhz to 866.67mhz and from 975mhz to 1,300mhz ? four power-up default frequencies (see part number order codes), re-programmable by i 2 c ? i 2 c programming interface for the output clock frequency and internal pll control registers ? frequency programming resolution is 435.9hz n ? one 2.5v, 3.3v lvpecl clock output ? two control inputs for the power-up default frequency ? lvcmos/lvttl compatible control inputs ? rms phase jitter @ 156.25mhz (12khz - 20mhz): 0.244ps (typical), integer pll feedback configuration ? rms phase jitter @ 156.25mhz (1khz - 40mhz): 0.265ps (typical), integer pll feedback configuration ? full 2.5v or 3.3v supply modes ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package IDT8N3Q001 10-lead ceramic 5mm x 7mm x 1.55mm package body cd package top view 8 v cc 7 nq 6 q fsel0 4 fsel1 5 10 sclk 9 sdata dnu 1 oe 2 v ee 3 pin assignment block diagram q ? nq osc f xtal mint, mfrac pfd & lpf femtoclock? ng vco 1950-2600mhz n i 2 c control configuration register (rom) ? (frequency, apr, polarity) 25 7 fsel1 fsel0 sclk sdata oe pulldown pulldown pullup pullup pullup p 2 www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 2 ?2012 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3a. oe configuration note: oe is an asynchronous control. table 3b. output frequency range note: supported output frequen cy range. the output frequency can be programmed to any frequency in this range and to a precision of 218hz or better. number name type description 1 dnu unused do not use. 2 oe input pullup output enable pin. see table 3 for function. lvcmos/lvttl interface levels. 3v ee power negative power supply. 5, 4 fsel1, fsel0 input pulldown default frequency select pins. see the default frequency order codes section. lvcmos/lvttl interface levels. 6, 7 q, nq output differential clock outpu t. lvpecl interface levels. 8 v cc power power supply pin. 9 sdata input/output pullup i 2 c data input/output. inpu t: lvcmos/lvttl compatible interface levels. output: open drain. 10 sclk input pullup i 2 c clock input. lvcmos/lvttl compatible interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 5.5 pf r pullup input pullup resistor 50 k ? r pulldown input pulldown resistor 50 k ? input output enable oe 0 outputs q, nq are in high-impedance state. 1 (default) outputs are enabled. 15.476mhz to 866.67mhz 975mhz to 1,300mmhz www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 3 ?2012 integrated device technology, inc. block diagram with programming registers q ? nq osc f xtal pfd & lpf femtoclock? ng vco 1950-2600mhz n i 2 c control sclk sdata fsel[1:0] oe pullup pullup pulldown pullup feedback divider m (25 bit) mint ? (7 bits) mfrac ? (18 bits) ? ? programming registers p0 mint0 mfrac0 n0 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits p1 mint1 mfrac1 n1 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits p2 mint2 mfrac2 n2 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits p3 mint3 mfrac3 n3 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits def (default): power-up defa ult register setting for i 2 c registers 00 01 10 11 34 34 34 34 34 7 27 7 30 30 30 30 18 output divider n pn, mintn, mfracn and nn 34 p 2 2 www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 4 ?2012 integrated device technology, inc. principles of operation the block diagram consists of the internal 3 rd overtone crystal and oscillator which provide the reference clock f xtal of either 114.285 mhz or 100mhz. the pll includes the femtoclock ng vco along with the pre-divider ( p ), the feedback divider ( m ) and the post divider ( n ). the p , m , and n dividers determine the output frequency based on the f xtal reference and must be configured correctly for proper operation. the feedback divider is fractional supporting a huge number of output frequencies. th e configuration of the feedback divider to integer-only values results in an improved output phase noise characteristics at the ex pense of the range of output frequencies. in addition, internal registers are used to hold up to four different factory pre-set p , m , and n configuration settings. these default pre-sets are stored in the i 2 c registers at power-up. each configuration is selected via the the fsel[1:0] pins and can be read back using the sclk and sdata pins. the user may choose to operate the device at an output frequency different than that set by the factory. after power-up, the user may write new p, n and m settings into one or more of the four configuration registers and then use the fsel[1:0] pins to select the newly programmed configuration. note that the i 2 c registers are volatile and a power supply cycle will reload the pre-set factory default conditions. if the user does choose to write a different p , m , and n configuration, it is recommended to write to a c onfiguration which is not currently selected by fsel[1:0] and then chan ge to that configuration after the i 2 c transaction has completed. c hanging the fsel[1:0] controls results in an immediate change of the output frequency to the selected register values. the p , m , and n frequency configurations support an output frequency range 15.476mhz to 866.67mhz and 975mhz to 1,300mhz. the devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. the relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. the output frequency is determined by the 2-bit pre-divider ( p ), the feedback divider (m) and th e 7-bit post divider ( n ). the feedback divider ( m ) consists of both a 7-bit integer portion ( mint ) and an 18-bit fractional portion ( mfrac ) and provides the means for high-resolution frequency generatio n. the output frequency f out is calculated by: the four configuration registers for the p, m (mint & mfrac) and n dividers which are named pn, mintn, mfracn and nn with n=0 to 3. ?n? denominates one of the four possible configurations. as identified previously, the configurations of p, m (mint & mfrac) and n divider settings are stored the i 2 c register, and the configuration loaded at power-up is determined by the fsel[1:0] pins. frequency configuration an order code is assigned to each frequency configuration programmed by the factory (d efault frequencies). for more information on the available default frequencies and order codes, please see the ordering information section in this document. for available order codes, see the femtoclock ng ceramic-package xo and vcxo ordering product information document. for more information and guidelines on programming of the device for custom frequency configurations , the register description, the selection of fractional and inte ger-feedback configurations and the serial interface description, see the femtoclock ng ceramic 5x7 module programming guide. f out f xtal 1 pn ? ----------- - mint mfrac 0.5 + 2 18 ---------------------------------- - + ?? = (1) table 4. frequency selection input selects register fsel1 fsel0 0 (def.) 0 (def.) frequency 0 p0, mint0, mfrac0, n0 0 1 frequency 1 p1, mint1, mfrac1, n1 1 0 frequency 2 p2, mint2, mfrac2, n2 1 1 frequency 3 p3, mint3, mfrac3, n3 www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 5 ?2012 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. ? these ratings are stress specifications only. functional operat ion of product at these condit ions or any conditions beyond ? those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ? extended periods may affect product reliability . ? dc electrical characteristics table 5a. power supply dc characteristics,v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 5b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 5c. lvcmos/lvttl dc characteristic, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 3.63v inputs, v i -0.5v to v cc + 0.5v outputs, i o (sdata) outputs, i o (lvpecl) ? continuous current ? surge current 10ma ? ? 50ma ? 100ma package thermal impedance, ? ja 49.4 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v i ee power supply current 140 ma symbol parameter test conditions minimum typical maximum units v cc supply voltage 2.375 2.5 2.625 v i ee power supply current 136 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage fsel[1:0], oe v cc =3.3v +5% 1.7 v cc +0.3 v fsel[1:0], oe v cc =2.5v +5% 1.7 v cc +0.3 v v il input low voltage fsel[1:0] v cc =3.3v +5% -0.3 0.5 v oe v cc =3.3v +5% -0.3 0.8 v fsel[1:0] v cc =2.5v +5% -0.3 0.5 v oe v cc =2.5v +5% -0.3 0.8 v i ih input ? high current oe v cc = v in = 3.465v or 2.625v 10 a sdata, sclk v cc = v in = 3.465v or 2.625v 5 a fsel0, fsel1 v cc = v in = 3.465v or 2.625v 150 a i il input ? low current oe v cc = 3.465v or 2.625v, v in = 0v -500 a sdata, sclk v cc = 3.465v or 2.625v, v in = 0v -150 a fsel0, fsel1 v cc = 3.465v or 2.625v, v in = 0v -5 a www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 6 ?2012 integrated device technology, inc. table 5d. lvpecl dc ch aracteristics, v cc = 3.3v 5% or v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v. ac electrical characteristics table 6. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.8 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.5 v v swing peak-to-peak output voltage swing 0.55 1.0 v symbol parameter test conditions minimum typical maximum units f out output frequency q, nq output divider, n = 3 to126 15.476 866.67 mhz output divider, n = 2 975 1,300 mhz f i initial accuracy measured at 25c 10 ppm f s temperature stability option code = a or b 100 ppm option code = e or f 50 ppm option code = k or l 20 ppm f a aging frequency drift over 10 year life 3 ppm frequency drift over 15 year life 5 ppm f t total stability option code a or b (10 year life) 113 ppm option code e or f (10 year life) 63 ppm option code k or l (10 year life) 33 ppm t jit(cc) cycle-to-cycle jitter; note 1 20 ps t jit(per) rms period jitter; note 1 2.85 4 ps t jit(?) rms phase jitter (random); ? fractional pll feedback and ? f xtal =100.000mhz (2xxx order ? codes) 17 mhz ?? f out ?? 1300mhz, note 2,3,4 0.440 0.995 ps rms phase jitter (random); ? integer pll feedback and ? f xtal =100.00mhz (1xxx order codes) 500 mhz ?? f out ?? 1300mhz, note 2,3,4 0.240 0.390 ps 125 mhz ?? f out ?? 500mhz, note 2,3,4 0.245 0.425 ps 17 mhz ?? f out ?? 125mhz, note 2,3,4 0.350 0.555 ps f out ?? 156.25mhz, note 2, 3, 4 0.244 ps f out ?? 156.25mhz, note 2, 3, 5 0.265 ps rms phase jitter (random) ? fractional pll feedback and ? f xtal =114.285mhz (0xxx order codes) 17 mhz ?? f out ?? 1300 mhz, note 2, 3, 4 0.475 0.990 ps ? n (100) single-side band phase noise, ? 100hz from carrier 156.25mhz -94.7 dbc/hz ? n (1k) single-side band phase noise, ? 1khz from carrier 156.25mhz -121.3 dbc/hz ? n (10k) single-side band phase noise, ? 10khz from carrier 156.25mhz -131.1 dbc/hz www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 7 ?2012 integrated device technology, inc. note: electrical parameters are guaranteed over the specified ambient operating temp erature range, which is established when th e device is mounted in a test socket with maintained tr ansverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. ? note: xtal parameters (initial accuracy, temperature stabilit y, aging and total stability) ar e guaranteed by manufacturing. note 1: this parameter is defined in accordance with jedec standard 65. note 2: please refer to the phase noise plots. note 3: please see the femtoclockng ceramic 5x7 modules progr amming guide for more information on pll feedback modes and the optimum configuration for phase noise. integer pll feedback is the default operation for the dddd = 1xxx order codes and config ures dsm_ena = 0 and adc_en = 0. note 4: integration range: 12khz-20mhz. note 5: integration range: 1khz-40mhz. ? n (100k) single-side band phase noise, ? 100khz from carrier 156.25mhz -137.3 dbc/hz ? n (1m) single-side band phase noise, ? 1mhz from carrier 156.25mhz -139.0 dbc/hz ? n (10m) single-side band phase noise, ? 10mhz from carrier 156.25mhz -154.9 dbc/hz psnr power supply noise rejection 50mv sinusoidal noise 1khz - 50khz -54 db t r / t f output rise/fall time 20% to 80% 100 425 ps odc output duty cycle 45 55 % t startup oscillator start-up time 20 ms t set output frequency settling time after fsel0 and fsel1 values are changed 470 s symbol parameter test conditions minimum typical maximum units www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 8 ?2012 integrated device technology, inc. typical phase noise at 156.25mhz (12khz - 20mhz) noise power dbc ? hz offset frequency (hz) note: rms phase noise (random) for integer pll feedback and f xtal =100.000mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 9 ?2012 integrated device technology, inc. parameter measureme nt information 3.3v lvpecl output load ac test circuit rms phase jitter output rise/fall time 2.5v lvpecl output load ac test circuit period jitter cycle-to-cycle jitter scope qx nqx v ee v cc -1.3v0.165v 2v offset frequency f 1 f 2 phase noise plot r ms jitter = area under curve defined by the offset frequency marke rs noise power 20% 80% 80% 20% t r t f v swing nq q scope qx nqx v ee v cc -0.5v 0.125v 2v v oh v re f v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram nq q ? ? ? ? t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 10 ?2012 integrated device technology, inc. parameter measure ment information, continued output duty cycle/pulse width/period applications information recommendations for unused input pins i nputs: lvcmos select pins the fsel[1:0] pins have internal pulldowns and oe control pins have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. sclk and sdata should be left floating if not used. t pw t period t pw t period odc = x 100% nq q www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 11 ?2012 integrated device technology, inc. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible ou tputs. therefor e, terminating resistors (dc current pa th to ground) or curre nt sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 1a and 1b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommend ed that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 1a. 3.3v lvpecl output termination figure 1b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 r2 50 rtt z o = 50 z o = 50 + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 r2 84 3.3v r3 125 r4 125 z o = 50 z o = 50 lvpecl inp ut 3.3v 3 .3v + _ www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 12 ?2012 integrated device technology, inc. termination for 2.5v lvpecl outputs figure 2a and figure 2b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 2b can be eliminated and the termination is shown in figure 2c. figure 2a. 2.5v lvpecl dr iver termination example figure 2c. 2.5v lvpecl dr iver termination example figure 2b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ? www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 13 ?2012 integrated device technology, inc. schematic layout figure 3 shows an example of IDT8N3Q001 application schematic. in this example, the device is operated at v cc = 3.3v. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter per formance, power supply isolation is required. the IDT8N3Q001 provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed fo r wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. figure 3. IDT8N3Q001 application schematic zo = 50 ohm nq r7 50 ru 2 not i nst all sc lk r3 13 3 sd at a logic control input e xampl es fsel1 r1 sp vc c + - b l m1 8b b2 21 sn 1 ferrit e bead 1 2 ru 1 1k rd 1 not i nst all q vcc 3.3v r2 sp r6 82.5 c3 0. 1 uf vcc oe 3.3v to logic input pins set logic input to '0' fsel0 r4 133 vcc zo = 50 ohm r9 50 r5 82 . 5 c1 0. 1 uf opt i onal y-termination r8 50 to logic input pins c2 10uf set logi c input to '1' zo = 50 ohm u1 1 2 3 6 7 8 4 5 9 10 dnu oe vee q nq vcc fsel0 fsel1 sdata sclk vcc=3.3v + - rd 2 1k zo = 50 ohm www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 14 ?2012 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the IDT8N3Q001. ? equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8N3Q001 is the sum of the core power plus the power dissipated in the load(s). ? the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 140ma = 485.1mw ? power (outputs) max = 34.2mw/loaded output pair ? total power_ max (3.465v, with all outputs sw itching) = 485.1mw + 34.2mw = 519.3mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temp erature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, th e appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 49.4c/w per table 7 below. therefore, tj for an ambi ent temperature of 85c with all outputs switching is: 85c + 0.519w * 49.4c/w = 110.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 10 lead ceramic 5mm x 7mm package, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 49.4c/w 44.2c/w 41c/w www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 15 ?2012 integrated device technology, inc. 3. calculations and equations. the purpose of this section is to calculate the power dissipa tion for the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 4. figure 4. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.8v ? (v cc_max ? v oh_max ) = 0.8v ? for logic low, v out = v ol_max = v cc_max ? 1.5v ? (v cc_max ? v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = ? [(2v ? 0.8v)/50 ? ] * 0.8v = 19.2mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = ? [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 34.2mw v out v cc v cc - 2v q1 rl 50 www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 16 ?2012 integrated device technology, inc. reliability information table 8. ? ja vs. air flow table for a 10-lead ceramic 5mm x 7mm package note: for proper thermal dissipation, the pcb layout for the pin pad should at minimum equal the package pin dimensions. transistor count the transistor count for id t8n3q001 rev g is: 47,372 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 49.4c/w 44.2c/w 41c/w www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 17 ?2012 integrated device technology, inc. package outline and package dimensions www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 18 ?2012 integrated device technology, inc. ordering information for femtoclock ng ceramic-package xo and vcxo products the programmable vcxo and xo devices support a variety of devices options such as the output type, number of default frequen- cies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. the device options, default frequencies and default vcxo pull range must be specified at the time of order and are programmed by idt before the shipment. shown below are the available order codes, including the device options and default frequency confi gurations. example part number: the order code 8n3qv01fg-0001cdi specifies a programmable, quad default-frequency vcxo with a voltage supply of 2.5v, a lvpecl output, a ? 50 ppm crystal frequency accuracy, contains a 114.285mhz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 rohs) 10-lead ceramic 5mm x 7mm x 1.55mm package and is fact ory-programmed to the default frequencies of 100mhz, 122.88mhz, 125mhz and 156.25mhz and to the vcxo pull range of minimum ? 100 ppm. other default frequencies and order codes are available from idt on request. for more information on available default frequencies, see the femtoclock ng ceramic-package xo and vcxo ordering product information document. shipping package 8 : tape & reel ? (no letter): tray ambient temperature range ? i ?: industrial: (t a = -40c to 85c) ? (no letter) : (t a = 0c to 70c) package code cd : lead-free, 6/10-lead ceramic 5mm x 7mm x 1.55mm die revision g option code (supply voltage and frequency-stability) a : v cc = 3.3v5%, 100ppm ? b : v cc = 2.5v5%, 100ppm ? e : v cc = 3.3v5%, 50ppm ? f : v cc = 2.5v5%, 50ppm ? k : v cc = 3.3v5%, 20ppm ? l : v cc = 2.5v5%, 20ppm default-frequency and vcxo pull range see document femtoclock ng ceramic- package xo and vcxo ordering product information. last digit = l : configuration pre-programmed and not changable dddd f xtal (mhz) pll feedback use for 0000 to 0999 114.285 fractional vcxo, xo 1000 to 1999 100.000 integer xo 2000 to 2999 fractional xo femtoclock ng i/o identifier 0 : lvcmos ? 3 : lvpecl ? 4 : lvds number of default frequencies s : 1: single ? d : 2: dual ? q : 4: quad part number function #pins oe fct. at pin 001 xo 10 oe@2 003 xo 10 oe@1 v01 vcxo 10 oe@2 v03 vcxo 10 oe@1 v75 vcxo 6 oe@2 v76 vcxo 6 noe@2 v85 vcxo 6 ? 085 xo 6 oe@1 270 xo 6 oe@1 271 xo 6 oe@2 272 xo 6 noe@2 273 xo 6 noe@1 8n x x xxx x x - dddd xx x x part order/number www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 19 ?2012 integrated device technology, inc. table 9. device marking marking industrial temperature range (t a = -40c to 85c) commercial temperature range (t a = 0c to 70c) idt8n3 x 001 y g- ? dddd cdi idt8n3 x 001 y g- ? dddd cd x = number of default frequencies, y = option code, dddd =default-frequency and vcxo pull range while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or spec ifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments. www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo IDT8N3Q001gcd revision a march 6, 2012 20 ?2012 integrated device technology, inc. revision history sheet rev table page description of change date a 9 19 table 9 device marking, corrected marking. 3/6/12 www.datasheet.co.kr datasheet pdf - http://www..net/
IDT8N3Q001 rev g data sheet quad-frequency programmable-xo disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is subj ect to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property righ ts of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution www.datasheet.co.kr datasheet pdf - http://www..net/

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